AN2824 STM32F10xxx I2C optimized ...AN2824 STM32F10xxx I2C optimized examples, STM32
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AN2824 Application note STM32F10xxx I 2 C optimized examples Introduction The aim of this application note is to provide I 2 C firmware optimized examples based on polling, interrupts and DMA, covering the four I 2 C communication modes available in the STM32F10xxx, that is, slave transmitter, slave receiver, master transmitter and master receiver and to provide recommendations on the correct use of the I 2 C peripheral. This application note applies to STM32F101xx and STM32F103xx medium, high and XL density microcontrollers, STM32F105/107xx connectivity line and STM32F100xx value line devices. Throughout this document, these devices are referred to collectively as STM32F10xxx. The application note is organized in three parts. The first part describes the I2C master programming examples using Polling, DMA and Interrupts. The second part describes the I2C slave programming examples using DMA and Interrupts. The third part is an overview of the content of the firmware accompanying this application note. . June 2010 Doc ID 15021 Rev 4 1/16 Contents AN2824 Contents 1 I2C master programming examples (DMA, interrupts, polling) . . . . . . 5 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Description of the examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.3 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 I2C slave programming examples (DMA, interrupt) . . . . . . . . . . . . . . . 12 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Description of the examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Firmware overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 Doc ID 15021 Rev 4 AN2824 List of tables List of tables Table 1. List of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Doc ID 15021 Rev 4 3/16 List of figures AN2824 List of figures Figure 1. Flowchart of master receiving more than 2 bytes using polling . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Flowchart of master receiving 1 or 2 bytes using polling . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Flowchart of master transmitter using polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Flowchart of master receiver using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Flowchart of master transmitter using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4/16 Doc ID 15021 Rev 4 AN2824 I2C master programming examples (DMA, interrupts, polling) 1 I2C master programming examples (DMA, interrupts, polling) 1.1 Overview The purpose of this section is to describe the firmware examples of I2C master transmitting and receiving data using polling, DMA and interrupts, provided with this application note. Flowcharts of Master Transmitter/Receiver in all modes (DMA, Polling, Interrupts) are also provided. You can modify these examples to adapt them to your application requirements. 1.2 Description of the examples 1.2.1 Polling Master receiver The master sends the START condition on the bus by setting START bit. The interface waits for the SB flag to be set and then cleared by writing the slave address in the DR register. The interface waits for the ADDR flag to be set then cleared by reading the SR1 and SR2 status register. After that, the master waits for the RXNE flag to be set in order to read data from the data register (EV7). The EV7 software sequence must complete before the end of the current byte transfer. In case EV7 software sequence can not be managed before the current byte end of transfer, it is recommended to use BTF instead. In order to close the communication, the software must guarantee the ACK bit is cleared in time in order to receive the last byte with a NACK. For this purpose, method 2 described in the device reference manuals is used: with this method, DataN_2 is not read, so that after DataN_1, the communication is stretched (both RxNE and BTF are set). Then: ● Clear the ACK bit before reading DataN-2 in DR to ensure it is cleared before the DataN Acknowledge pulse. ● After this, just after reading DataN_2, set the STOP/ START bit and read DataN_1. ● After RxNE is set, read DataN. This is illustrated below: When 3 bytes remain to be read: – RxNE = 1 => Nothing (DataN-2 not read). – DataN-1 received – BTF = 1 because both shift and data registers are full: DataN-2 in DR and DataN-1 in the shift register => SCL tied low: no other data will be received on the bus. – Clear ACK bit – Read DataN-2 in DR => This starts DataN reception in the shift register. – DataN received (with a NACK) – Program START/STOP – Read DataN-1 Doc ID 15021 Rev 4 5/16 [ Pobierz całość w formacie PDF ] |
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