AT49F001NAT49F001N, Aplikacje data
[ Pobierz całość w formacie PDF ]
Features • Single Voltage Operation – 5V Read – 5V Reprogramming • Fast Read Access Time - 55 ns • Internal Program Control and Timer • Sector Architecture – One 16K Byte Boot Block with Programming Lockout – Two 8K Byte Parameter Blocks – Two Main Memory Blocks (32K, 64K) Bytes • Fast Erase Cycle Time - 10 seconds • Byte By Byte Programming - 10 m s/Byte Typical • Hardw are Data Protection • DATA Polling for End of Program Detection • Low Power Dissipation – 50 mA Active Current – 100 m A CMOS Standby Current • Typical 10,000 Write Cycles 1-Megabit (128K x 8) 5-volt Only Flash Memory Description The AT49F001(N)(T) is a 5-volt-only in-system reprogrammable Flash Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. AT49F001 AT49F001N AT49F001T AT49F001NT (continued) Pin Configurations DIP Top View Pin Name Function * RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A0 - A16 Addresses CE Chip Enable OE Output Enable WE Write Enable RESET RESET I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect VSOP Top View (8 x 14 mm) or TSOP Top View (8 x 20 mm) Type 1 PLCC Top View A11 A9 A8 A13 A14 NC WE VCC * RESET A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 Rev. 1008B–07/98 *Note: This pin is a DC on the AT49F001N(T). 1 When the device is deselected, the CMOS standby current is less than 100 The device is erased by executing the erase command sequence; the device internally controls the erase opera- tions. There are two 8K byte parameter block sections and two main memory blocks. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the fea- ture is enabled, the boot sector is protected from being reprogrammed. In the AT49F001N(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49F001(T), once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less. A. For the AT49F001NT pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package are don’t connect pins. To allow for simple in-system reprogrammability, the AT49F001(N)(T) does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the de vice is s imilar to r eading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus conten- tion. Reprogramming the AT49F001(N)(T) is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 50 m s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or pro- gram can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. m Block Diagram AT49F001(N) DATA INPUTS/OUTPUTS I/O7 - I/O0 AT49F001(N)T DATA INPUTS/OUTPUTS I/O7 - I/O0 V CC GND 8 8 INPUT/OUTPUT BUFFERS INPUT/OUTPUT BUFFERS OE WE CE RESET CONTROL LOGIC PROGRAM DATA LATCHES PROGRAM DATA LATCHES Y DECODER Y-GATING Y-GATING 1FFFF 1FFFF ADDRESS INPUTS MAIN MEMORY BLOCK 2 (64K BYTES) BOOT BLOCK (16K BYTES) X DECODER 1C000 1BFFF 10000 0FFFF PARAMETER BLOCK 1 (8K BYTES) MAIN MEMORY BLOCK 1 (32K BYTES) 1A000 19FFF 08000 07FFF PARAMETER BLOCK 2 (8K BYTES) PARAMETER BLOCK 2 (8K BYTES) 18000 17FFF 06000 05FFF MAIN MEMORY BLOCK 1 (32K BYTES) PARAMETER BLOCK 1 (8K BYTES) 10000 0FFFF 04000 03FFF MAIN MEMORY BLOCK 2 (64K BYTES) BOOT BLOCK (16K BYTES) 00000 00000 AT49F001(N)(T) 2 AT49F001(N)(T) Device Operation READ : Th e A T49F 001(N)(T) is acc essed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. T he ou tpu ts are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus conten- tion. COMMAND SEQUENCES: When the device is first pow- ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The comma nd s eq uen ces are wr itte n b y ap plying a low pulse on th e W E or CE input with CE or WE low (respec- tively) a nd O E high . The address is latched on the falling edge of CE or WE, whichever oc curs las t. T he data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address loca- tions used in the command sequences are not affected by entering th e comm and sequences. RESET: A RESET input pin is p rovided to ease some sys- tem applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outp uts of the device in a high impedence state. If the RESET pin makes a high to low transition during a program or erase operation, the operation may not be sucessfully completed and the operatio n will ha ve to be repeated after a high level is applie d to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control i nputs. By applying a 12V CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Mem- ory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. SECTOR ERASE : As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections can be independently erased and repro- grammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the other block should be erased and reprogrammed before the first block is again erased. The Sector Erase command is a six bus c ycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising ed ge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can con- vert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The pro gram cy cle has addresses latched on the falling edge of WE or CE, whichev er o cc urs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Progr ammin g is completed after the specified t BP cycle time. The DATA polling feature may also be used to indi- cate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti- vated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000 to 03FFF for the AT49F001(N) while the address 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available for the AT49F001N(T). ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is t EC . If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. ± 3 range of the boot block is 1C000 to 1FFFF for the AT49F001(N)T. Once the feature is enabled, the data in the boot block can no longer be erased or programmed with input voltage lev- els of 5.5V or less. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program com- mands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the soft- ware product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out for the AT49F001(N) and a read from address 1C002H will show if programming the boot block is locked out for the AT49F001(N)T. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identi- fication exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts. By doing this, pro- tected boot block data can be altered through a chip e rase, sector erase or word programming. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. This feature is not available on the AT49F001N(T). PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F001(N)(T) features DATA polling to indicate the end of a program cycle. During a pro- gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the pro gram cy cle. TOGGLE BIT: In addition to DATA polling the AT49F001(N)(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop tog- gling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F001(N)(T) in the following ways: (a) V CC sense: if V CC is below 3.8V (typical), the program func tion is in hib- ited. (b) Pro gram inhibit: holding any one of OE low, CE high or WE high inhibits program cycles . (c ) N oise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. AT49F001(N)(T) 4 AT49F001(N)(T) Command Definition (in Hex) (1) 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Command Sequence Bus Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 SA (4) Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 30 Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D IN Boot Block Lockout (2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (3) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit (3) 1 XXXX F0 Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex) 2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F001(N) and 1C000H to 1FFFFH for the AT49F001(N)T. 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses For the AT49F001(N): SA = 10000 to 1FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 04000 to 05FFF for PARAMETER BLOCK 1 SA = 06000 to 07FFF for PARAMETER BLOCK 2 SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2 For the AT49F001(N)T: SA = 1C000 to 1FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 1A000 to 1BFFF for PARAMETER BLOCK 1 SA = 18000 to 19FFF for PARAMETER BLOCK 2 SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to V CC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V 5 [ Pobierz całość w formacie PDF ] |
Podobne
|