Atmel ATxmega A3Atmel ATxmega A3, Mechatronika (Elektronika, Mechanika, Obwody elektryczne), MPP - Mobilna Platforma Pomiarowa, ...
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Features • High-performance, Low-power 8/16-bit Atmel ® AVR ® XMEGA TM Microcontroller Non-volatile Program and Data Memories – 64 KB - 256 KB of In-System Self-Programmable Flash – 4 KB - 8 KB Boot Code Section with Independent Lock Bits – 2 KB - 4 KB EEPROM – 4 KB - 16 KB Internal SRAM Peripheral Features – Four-channel DMA Controller with support for external requests – Eight-channel Event System – Seven 16-bit Timer/Counters Four Timer/Counters with 4 Output Compare or Input Capture channels Three Timer/Counters with 2 Output Compare or Input Capture channels High Resolution Extensions on all Timer/Counters Advanced Waveform Extension on one Timer/Counter – Seven USARTs IrDA Extension on 1 USART – AES and DES Crypto Engine – Two Two-wire Interfaces with dual address match (I 2 C and SMBus compatible) – Three SPI (Serial Peripheral Interfaces) – 16-bit Real Time Counter with Separate Oscillator – Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters – One Two-channel, 12-bit, 1 Msps Digital to Analog Converter – Four Analog Comparators with Window compare function – External Interrupts on all General Purpose I/O pins – Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal and External Clock Options with PLL – Programmable Multi-level Interrupt Controller – Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby – Advanced Programming, Test and Debugging Interfaces JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming PDI (Program and Debug Interface) for programming, test and debugging I/O and Packages – 50 Programmable I/O Lines – 64-lead TQFP – 64-pad QFN Operating Voltage – 1.6 – 3.6V Speed performance – 0 – 12 MHz @ 1.6 – 3.6V – 0 – 32 MHz @ 2.7 – 3.6V 8/16-bit XMEGA A3 Microcontroller ATxmega256A3 ATxmega192A3 ATxmega128A3 ATxmega64A3 Typical Applications Industrial control Climate control Hand-held battery applications Factory automation ZigBee Power tools Building control Motor control HVAC Board control Networking Metering White Goods Optical Medical Applications 8068T–AVR–12/10 XMEGA A3 1. Ordering Information E 2 Package (1)(2)(3) Ordering Code Flash SRAM Speed (MHz) Power Supply Temp ATxmega256A3-AU 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V ATxmega192A3-AU 192 KB + 8 KB 2 KB 16 KB 32 1.6 - 3.6V 64A ATxmega128A3-AU 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V ATxmega64A3-AU 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V -40 ° C - 85 ° C ATxmega256A3-MH 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V ATxmega192A3-MH 192 KB + 8 KB 2 KB 16 KB 32 1.6 - 3.6V 64M2 ATxmega128A3-MH 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V ATxmega64A3-MH 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see ”Packaging information” on page 61 . Package Type 64A 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64M2 64-Pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN) 2 8068T–AVR–12/10 XMEGA A3 2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout. INDEX CORNER PA 3 PA 4 PA 5 PA 6 PA 7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND VCC PC0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF2 PF1 PF0 VCC GND PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 VCC GND PD7 Por t R DATA BU S ADC A OSC/CLK Control BOD VREF POR AC A0 TEMP RTC OCD Power Control FLASH AC A1 CPU RAM ADC B Reset Control DMA E 2 PROM DAC B AC B0 Interrupt Controller Watchdog AC B1 Event System ctrl DATA BU S EVENT ROUTING NETWORK Por t C Por t D Por t E Por t F Notes: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 49 . 2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. 3 8068T–AVR–12/10 XMEGA A3 3. Overview The Atmel ® AVR ® XMEGA ™ A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conven- tional single-accumulator or CISC based microcontrollers. The XMEGA A3 devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Periph- eral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this can also be used for On-chip Debug and programming. The XMEGA A3 devices have five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all peripherals to continue functioning. The Power-down mode saves the SRAM and register contents but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows very fast start-up from external crystal combined with low power consump- tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further reduce power consumption, the peripheral clock for each individual peripheral can optionally be stopped in Active mode and Idle sleep mode. The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro- gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader running in the device can use any interface to download the application program to the Flash memory. The Bootloader software in the Boot Flash section will continue to run while the Appli- cation Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a power- ful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The XMEGA A3 devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 4 8068T–AVR–12/10 XMEGA A3 3.1 Block Diagram Figure 3-1. XMEGA A3 Block Diagram PR[0..1] X TA L 1 XTAL2 Oscillator Circuits/ Clock Generation Watchdog Oscillator Real Time Counter Watchdog Timer DATA BUS PA[0..7] PORT A (8) Power Supervision POR/BOD & RESET VCC Event System Controller Oscillator Control ACA GND SRAM DMA Controller Sleep Controller RESET/ PDI_CLK ADCA PDI PDI_DATA AREFA BUS Controller Prog/Debug Controller VCC/10 JTAG PORT B Int. Ref. Tempref DES OCD AREFB CPU Interrupt Controller AES ADCB ACB NVM Controller USARTF0 PB[0..7]/ JTAG PORT B (8) TCF0 PF[0..7] Flash EEPROM DACB IRCOM DATA BUS EVENT ROUTING NETWORK To Clock Generator PORT C (8) PORT D (8) PORT E (8) TO SC1 TOSC2 PC[0..7] PD[0..7] PE[0..7] 5 8068T–AVR–12/10 [ Pobierz całość w formacie PDF ] |
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