ATtiny26lATtiny26l, Noty katalogowe
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Features • High-performance, Low-power AVR ® 8-bit Microcontroller RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz Data and Non-volatile Program Memory – 2K Bytes of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – 8-bit Timer/Counter with Separate Prescaler – 8-bit High-speed Timer with Separate Prescaler 2 High Frequency PWM Outputs with Separate Output Compare Registers Non-overlapping Inverted PWM Output Pins – Universal Serial Interface with Start Condition Detector – 10-bit ADC 11 Single Ended Channels 8 Differential ADC Channels 7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) – On-chip Analog Comparator – External Interrupt – Pin Change Interrupt on 11 Pins – Programmable Watchdog Timer with Separate On-chip Oscillator Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power-down Modes – Power-on Reset and Programmable Brown-out Detection – External and Internal Interrupt Sources – In-System Programmable via SPI Port – Internal Calibrated RC Oscillator I/O and Packages – 20-lead PDIP/SOIC: 16 Programmable I/O Lines – 32-lead QFN/MLF: 16 programmable I/O Lines Operating Voltages – 2.7V - 5.5V for ATtiny26L – 4.5V - 5.5V for ATtiny26 Speed Grades – 0 - 8 MHz for ATtiny26L – 0 - 16 MHz for ATtiny26 Power Consumption at 1 MHz, 3V and 25 ° C for ATtiny26L – Active 16 MHz, 5V and 25 ° C: Typ 15 mA – Active 1 MHz, 3V and 25 ° C: 0.70 mA – Idle Mode 1 MHz, 3V and 25 ° C: 0.18 mA – Power-down Mode: < 1 µA 8-bit Microcontroller with 2K Bytes Flash ATtiny26 ATtiny26L Not recommended for new designs 1477J–AVR–06/07 Pin Configuration PDIP/SOIC (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/ OC1A ) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/I NT0/T0 ) PB6 (ADC10/RESET) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC PA4 (ADC3) PA5 (ADC4) PA6 (ADC5/AIN0) PA7 (ADC6/AIN1) MLF Top View NC (OC1B) PB3 NC VCC GND NC (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 NC PA2 (ADC2) PA3 (AREF) GND NC NC AVCC PA4 (ADC3) Note: The bottom pad under the QFN/MLF package should be soldered to ground. 2 ATtiny26(L) 1477J–AVR–06/07 ATtiny26(L) Description The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny26(L) has a high precision ADC with up to 11 single ended channels and 8 differential channels. Seven differential channels have an optional gain of 20x. Four out of the seven differential channels, which have the optional gain, can be used at the same time. The ATtiny26(L) also has a high frequency 8-bit PWM module with two independent outputs. Two of the PWM outputs have inverted non-overlapping output pins ideal for synchronous rectifica- tion. The Universal Serial Interface of the ATtiny26(L) allows efficient software implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features allow for highly integrated battery charger and lighting ballast applications, low-end ther- mostats, and firedetectors, among other applications. The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital Converter with two differential voltage input gain stages, and four software selectable power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode, only the ADC is functioning. The Power-down mode saves the register contents but freezes the oscillators, disabling all other chip functions until the next interrupt or hard- ware reset. The Standby mode is the same as the Power-down mode, but external oscillators are enabled. The wakeup or interrupt on pin change features enable the ATtiny26(L) to be highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode. The device is manufactured using Atmel’s high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATtiny26(L) AVR is supported with a full suite of program and system development tools including: Macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits. 3 1477J–AVR–06/07 Block Diagram Figure 1. The ATtiny26(L) Block Diagram VCC 8-BIT DATA BUS INTERNAL INTERNAL OSCILLATOR CALIBRATED OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL PROGRAM FLASH SRAM MCU CONTROL REGISTER AVCC INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS MCU STATUS REGISTER X TIMER/ COUNTER0 INSTRUCTION DECODER Y Z TIMER/ COUNTER1 CONTROL LINES ALU UNIVERSAL SERIAL INTERFACE STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC ISP INTERFACE EEPROM OSCILLATORS DATA REGISTER PORT A DATA DIR. REG.PORT A ADC DATA REGISTER PORT B DATA DIR. REG.PORT B PORT A DRIVERS PORT B DRIVERS PA0-PA7 PB0-PB7 4 ATtiny26(L) 1477J–AVR–06/07 ATtiny26(L) Pin Descriptions VCC Digital supply voltage pin. GND Digital ground pin. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to V CC , even if the ADC is not used. If the ADC is used, it should be connected to V CC through a low-pass filter. See page 96 for details on operating of the ADC. Port A (PA7..PA0) Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs for the ADC and analog comparator and pin change interrupt as described in “Alternate Port Functions” on page 48. Port B (PB7..PB0) Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide inter- nal pull-ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin PB7 as an I/O pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and pin change interrupt as described in “Alternate Port Functions” on page 48. An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. 5 1477J–AVR–06/07 [ Pobierz całość w formacie PDF ] |
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