Attiny 2313 opisAttiny 2313 opis, Mikrokontrolery
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Features • Utilizes the AVR ® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 24 MIPS Throughput at 24 MHz • Data and Non-volatile Program and Data Memories – 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles – 128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – USI – Universal Serial Interface – Full Duplex USART • Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, and 32-pin MLF • Operating Voltages – 1.8 - 5.5V (ATtiny2313) • Speed Grades – ATtiny2313V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V – ATtiny2313: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V • Power Consumption Estimates – Active Mode 1 MHz, 1.8V: 300 µA 32 kHz, 1.8V: 20 µA (including oscillator) – Power-down Mode < 0.2 µA at 1.8V 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny2313/V Preliminary Summary Rev. 2543DS–AVR–03/04 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. 2543DS–AVR–03/04 Pin Configurations Figure 1. Pinout ATtiny2313 PDIP/SOIC (RESET/dW)PA2 (RXD)PD0 (TXD)PD1 (XTAL2)PA1 (XTAL1)PA0 (CKOUT/XCK/INT0)PD2 (INT1)PD3 (T0)PD4 (OC0B/T1)PD5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC PB7(UCSK/SCK/PCINT7) PB6(DO/PCINT6) PB5(DI/SDA/PCINT5) PB4(OC1B/PCINT4) PB3(OC1A/PCINT3) PB2(OC0A/PCINT2) PB1(AIN1/PCINT1) PB0(AIN0/PCINT0) PD6(ICP) Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2 ATtiny2313/V 2543DS–AVR–03/04 ATtiny2313/V Block Diagram Figure 2. Block Diagram XTAL1 XTAL2 PA0 - PA2 PORTA DRIVERS VCC DATA REGISTER PORTA DATA DIR. REG. PORTA INTERNAL CALIBRATED OSCILLATOR 8-BIT DATA BUS INTERNAL OSCILLATOR OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL RESET PROGRAM FLASH SRAM MCU CONTROL REGISTER MCU STATUS REGISTER ON-CHIP DEBUGGER INSTRUCTION REGISTER GENERAL PURPOSE REGISTER TIMER/ COUNTERS INSTRUCTION DECODER INTERRUPT UNIT EEPROM CONTROL LINES ALU USI STATUS REGISTER PROGRAMMING LOGIC SPI USART DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD PORTB DRIVERS PORTD DRIVERS PB0 - PB7 PD0 - PD6 3 2543DS–AVR–03/04 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial program- mable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register con- tents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono- lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. 4 ATtiny2313/V 2543DS–AVR–03/04 ATtiny2313/V Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313 as listed on page 52. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny2313 as listed on page 52. Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313 as listed on page 55. RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 33. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1 is an alternate function for PA0. XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1. Figure 3. 5 2543DS–AVR–03/04 [ Pobierz całość w formacie PDF ] |
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