AT49F040AAT49F040A, elektronika, A ukł scsalone
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Features • Single-voltage Operation –5V Read – 5V Reprogramming • Fast Read Access Time – 55 ns • Internal Program Control and Timer • Sector Architecture – One 16K Bytes Boot Block with Programming Lockout – Two 8K Bytes Parameter Blocks – Eight Main Memory Blocks (One 32K Bytes, Seven 64K Bytes) • Fast Erase Cycle Time – 6 Seconds • Byte-by-Byte Programming – 20 µs/Byte Typical • Hardw are Data Protection • DATA Polling for End of Program Detection • Low Power Dissipation – 20 mA Active Current – 70 µA CMOS Standby Current • Typical 10,000 Write Cycles 4-megabit (512K x 8) 5-volt Only Flash Memory Description The AT49F040A is a 5-volt only in-system reprogrammable Flash memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 110 mW over the commercial temperature range. AT49F040A Pin Configurations DIP Top View Pin Name Function A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A0 - A18 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs PLCC Top View A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 TSOP Top View (8 x 20 mm) Type 1 A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 3359A–FLASH–6/03 1 When the device is deselected, the CMOS standby current is less than 70 µA. To allow for simple in-system reprogrammability, the AT49F040A does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the dev i ce. Readi ng d ata out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F040A is per- formed by erasing a block of data and then programming on a byte by byte basis. The byte pro gramm ing time is a fast 20 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The device is erased by executing the erase command sequence; the device internally con- trols the erase operations. There are two 8K byte parameter block sections, eight main memory blocks, and one boot block. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out fea- ture to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. Block Diagram AT49F040A DATA INPUTS/OUTPUTS I/O7 - I/O0 VCC GND 8 OE WE CE RESET CONTROL LOGIC INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING Y DECODER ADDRESS INPUTS MAIN MEMORY BLOCK 8 (64K BYTES) MAIN MEMORY BLOCK 7 (64K BYTES) MAIN MEMORY BLOCK 6 (64K BYTES) MAIN MEMORY BLOCK 5 (64K BYTES) 7FFFF X DECODER 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF MAIN MEMORY BLOCK 4 (64K BYTES) 30000 2FFFF MAIN MEMORY BLOCK 3 (64K BYTES) 20000 1FFFF MAIN MEMORY BLOCK 2 (64K BYTES) 10000 0FFFF MAIN MEMORY BLOCK 1 (32K BYTES) 08000 PARAMETER BLOCK 2 (8K BYTES) 07FFF 06000 05FFF PARAMETER BLOCK 1 (8K BYTES) 04000 03FFF BOOT BLOCK (16K BYTES) 00000 2 AT49F040A 3359A–FLASH–6/03 AT49F040A Device Operation READ: The AT49F040A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the addre ss p in s is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the C omm an d D efinitions t able . T he c ommand sequences ar e w ritten by applying a low pulse on the WE or CE input wit h C E or WE low (respectively) and OE high. The address is latched on the fa lling e dge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the com- mand sequences. ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase opera- tion so that no external clocks are required. The maximum time needed to erase the whole chip is t EC . If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1 - 8 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and eight main memory blocks. The 8K-byte parameter block sections and the eight main memory blocks can be independently erased and reprogrammed. The Sec tor E rase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data inp ut co mmand is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on th e fall ing ed ge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE , whic hever occurs first. Program- ming is completed after the specified t BP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. 3 3359A–FLASH–6/03 Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000 to 03FFF. Once the feature is enabled, the data in the boot block can no longer be erased or pro- grammed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Defini- tions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if pro- gramming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identi- fication exit code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and man- ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the com- plement of the loaded data on I/O7. Once the prog ram c ycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F040A provides another method for deter- mining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin- ing the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F040A in the following ways: (a) V CC sense: if V CC is belo w 3. 8V ( typical), the pro- gram function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or W E h igh inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 4 AT49F040A 3359A–FLASH–6/03 AT49F040A Command Definition (in Hex) (1) Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase 6 555 AA AAA (2) 55 555 80 555 AA AAA 55 555 10 Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA 30 Byte Program 4 555 AA AAA 55 555 A0 Addr D IN Boot Block Lockout (3) 6 555 AA AAA 55 555 80 555 AA AAA 55 555 40 Product ID Entry 3 555 AA AAA 55 555 90 Product ID Exit (4) 3 555 AA AAA 55 555 F0 Product ID Exit (4) 1 XXXX F0 Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows: A11 - A0 (Hex); A11 - A18 (don’t care). 2. Since A11 is don’t care, AAA can be replaced with 2AA. 3. The 16K byte boot sector has the address range 00000H to 03FFFH. 4. Either one of the Product ID Exit commands can be used. 5. SA = sector addresses: SA = 00000 to 03FFF for BOOT BLOCK SA = 04000 to 05FFF for PARAMETER BLOCK 1 SA = 06000 to 07FFF for PARAMETER BLOCK 2 SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1 SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2 SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 3 SA = 30000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 4 SA = 40000 to 4FFFF for MAIN MEMORY ARRAY BLOCK 5 SA = 50000 to 5FFFF for MAIN MEMORY ARRAY BLOCK 6 SA = 60000 to 6FFFF for MAIN MEMORY ARRAY BLOCK 7 SA = 70000 to 7FFFF for MAIN MEMORY ARRAY BLOCK 8 Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to V CC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V 5 3359A–FLASH–6/03 Storage Temperature ..................................... -65°C to +150°C [ Pobierz całość w formacie PDF ] |
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