AT91 ATMELAT91 ATMEL, elektronika, A ukł scsalone
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Connecting an I 2 S-Compatible Audio DAC to the AT91x40 Series Microcontrollers Introduction The purpose of this Application Note is to provide the procedure to construct the inter- face between a stereo audio digital-to-analog converter (DAC) and an AT91x40 Series Microcontroller (DocRef. 2). The stereo audio DAC of choice for this example, is the Micronas ® DAC 3550A device. The digital interface of such a device is usually I 2 S standard compliant. As the AT91x40 Series microcontrollers do not embed such a serial peripheral, a parallel to I 2 S serial interface has to be set up with a programmable logic device. This has been achieved with an ATMEL ATF1508ASV 128 Macrocells CPLD (DocRef. 3). This class of DAC embeds audio configuration registers that are accessible through a serial link. Because this peripheral is not embedded in the AT91x40 Series Microcon- trollers, the protocol must be established by software through Parallel Input/Output (PIO) lines (DocRef. 4). AT91 ARM ® Thumb ® Microcontrollers Application Note References The following sources contributed information to this Application Note 1. ATMEL AT91 ARM Thumb Microcontrollers AT91x40 Series Full Data-Sheet, Rev. 1354C-07/01 2. ATMEL High-performance EE PLD ATF1508ASV/ATF1508ASVL, Rev. 1408E- 09/00 3. AT91 TWI Drivers for AT24C512 Serial E 2 PROM, Rev. 1742A-04/01 Rev. 2646A–ATARM–05-02 1 Serialization The I 2 S (Inter-IC Sound) standard is based on a three-wire bus (DocRef. 1): • a continuous serial clock (sck), • a word select signal (ws) • a serial data line (sd) The device generating sck and ws (ie the CPLD in our application) is the master. The serial data (sd) is driven out from the master on the trailing edge of the serial clock (sck) and sampled by the audio DAC on the sck leading edge. The word select signal (ws) indicates the channel being transmitted: • ws = 0; left channel, • ws = 1; right channel. The access to the serializer is established through the AT91 External Bus Interface (EBI) peripheral. An interrupt signal is provided by this device to the microcontroller in order to alert the software that it must write the next audio data. To view the adopted I 2 S hardware configuration, please refer to the illustration in Figure 1 on page 3. The hardware connec- tions are illustrated in Figure 3 on page 4. In this application example, the 6.144MHz Quartz Crystal Oscillator sets the audio data sample rate to 48KHz. 2 AT91 ARM Thumb 2646A–ATARM–05-02 AT91 ARM Thumb I 2 S Hardware Block Diagram Figure 1. I 2 S Hardware Interface Block Diagram ATF1508ASV EBI_D[15:0] CLK CLK 74 LVC16374 74L VC16374 EBI_A1 EBI_A2 EBI_A3 Y0 Y1 Y2 74 LV138 E1 E2 E3 OE OE //// DATA LEFT //// DATA RIGHT CLK CLK EBI_NWE EBI_NCS EBI_CS 74 LVC163 7 4LVC163 WSD OE OE WSD CLK START LSB MSB EBI_D0 D Q DS D[0:15] 74L V7 4 CLR AT91_NRST Q //// CE Shift Registers SD SCK CP 74LV165 PL AT91_IRQ WS PRE WS CLR CLR WSP DQ DQ 16 74LV74 CLK 74LV74 Q CLK Q 6.144 MHz Quartz Crystal Oscillator CLR SCK SCK 4 Figure 2. Timing Diagram AT91_NRST START SCK WS SD MSB LSB MSB WSP 3 2646A–ATARM–05-02 A0 A1 A2 Figure 3. I 2 S Hardware Connections EBI AT91x40 CPLD I 2 S Bus I 2 S Stereo Audio DAC DAC 3550A Analog Outputs I 2 S IRQ ATF1508ASV 6.144 MHz Quartz Crystal Oscillator PIO TWI Bus 4 AT91 ARM Thumb 2646A–ATARM–05-02 AT91 ARM Thumb AT71508ASV CPLD VHDL Code The related CPLD VHDL Code is the following: -- ATMEL Microcontroller Software Support - ROUSSET - -- AT91 Audio Extension Card I2S Interface -- 1.0- 11/10/01- ED -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- library IEEE ; use IEEE.std_logic_1164.all ; -------------------------------------------------------------------------------------- -- Entity Section -------------------------------------------------------------------------------------- entity i2s_interface is port ( data: in std_logic_vector(15 downto 0); -- Data Bus address: in std_logic_vector(3 downto 1 ; -- Address Bus nrst, -- AT91 Reset Signal ncs, -- AT91 Chip Select Signal cs, -- AT91 Chip Select Signal nwe, -- AT91 Write Control Signal clock : in std_logic ; -- 6.144MHz Clock Input irq, -- AT91 Interrupt Signal dai, -- I2S Serial Data wsi, -- I2S Channel Word Select cli: out std_logic -- I2S Serial Clock ); end i2s_interface ; -------------------------------------------------------------------------------------- -- I2S Architecture Section -------------------------------------------------------------------------------------- architecture i2s of i2s_interface is signal left_data_select, -- left data chip select signal right_data_select, -- right data chip select signal run_command_select, -- start/stop command chip select start, -- Start/Stop Serializing Data sck, -- primary clock (6.144MHz) -- divided by 4 (1.536MHz) clk_int_sck, -- intermediate clock variable sck_1, -- left data register output enable command sck_2, -- right data register output enable command 5 2646A–ATARM–05-02 [ Pobierz całość w formacie PDF ] |
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