AT34C02AT34C02, Książki, polskie, elektronika i elektrotechnika, Układy scalone - baza, Uklady scalone baza, Baza
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Features • Permanent Software Write Protection for the First-half of the Array – Software Procedure to Verify Write Protect Status • Hardware Write Protection for the Entire Array • Low-voltage and Standard-voltage Operation – 5.0 (V CC = 4.5V to 5.5V) – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V) • Internally Organized 256 x 8 • 2-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 100 kHz (1.8V) and 400 kHz (2.7V and 5.0V) Compatibility • 16-byte Page Write Modes • Partial Page Writes Are Allowed • Self-timed Write Cycle (10 ms max) • High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3,000V • Automotive Grade and Extended Temperature Devices Available • 8-pin PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages 2-wire Serial EEPROM with Permanent Software Write Protect 2K (256 x 8) Description The AT34C02 provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a software write protection feature while hardware write pro- tection for the entire array is available via an external pin as well. Once the software write protection is enabled, by sending a special command to the device, it cannot be reversed. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the application. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT34C02 is available in space saving 8-pin PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, it is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), and 1.8V (1.8V to 5.5V) versions. AT3 4C0 2 2-Wire Serial EEPROM with Permanent Software Write Protec Pin Configurations 8-lead SOIC Pin Name Function A0 - A2 Address Inputs A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA SDA Serial Data SCL Serial Clock Input WP Write Protect 8-lead TSSOP 8-pin PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Rev. 0958G–09/00 1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125 °C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Block Diagram VCC GND WP SCL START STOP LOGIC SERIAL CONTROL LOGIC SDA EN WRITE PROTECT CIRCUITRY H.V. PUMP/TIMING LOAD DEVICE ADDRESS COMPARATOR COMP DATA RECOVERY LOAD INC SOFTWARE WRITE PROTECTED AREA (00H - 7FH) A 2 A 1 R/W DATA WORD ADDR/COUNTER A 0 EEPROM Y DEC SERIAL MUX D IN D OUT /ACK LOGIC D OUT Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT34C02. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). WRITE PROTECT (WP): The AT34C02 has a Write Pro- tect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when con- nected to ground (GND) or when left floating. When the Write Protect pin is connected to V CC , the write protection feature is enabled for the entire array. The write protection modes are shown in the following table. 2 AT34C02 AT34C02 AT34C02 Write Protection Modes WP Pin Status Write Protect Register Part of the Array Write Protected V CC — Full Array (2K) GND or Floating Not Programmed Normal Read/Write GND or Floating Programmed First-Half of Array (1K: 00H - 7FH) Pin Capacitance (1) Applicable over recommended operating range from T A = 25 ° C, f = 1.0 MHz, V CC = +1.8V Symbol Test Condition Max Units Conditions C I/O Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN Input Capacitance (A 0 , A 1 , A 2 , SCL) 6 pF V IN = 0V Note: 1. This parameter is characterized and is not 100% tested DC Characteristics Applicable over recommended operating range from: T AI = -40 ° C to +85 ° C, V CC = +1.8V to +5.5V, T AC = 0 ° C to +70 ° C, V CC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units V CC1 Supply Voltage 1.8 5.5 V V CC2 Supply Voltage 2.7 5.5 V V CC3 Supply Voltage 4.5 5.5 V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0 mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0 mA I SB1 Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0 µ A I SB2 Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0 µ A I SB3 Standby Current V CC = 5.0V V IN = V CC or V SS 8.0 18.0 µ A I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0 µ A I LO Output Leakage Current V OUT = V CC or V SS 0.05 3.0 µ A V IL Input Low Level (1) -0.6 V CC x 0.3 V V IH Input High Level (1) V CC x 0.7 V CC + 0.5 V V OL2 Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4 V V OL1 Output Low Level V CC = 1.8V I OL = 0.15 mA 0.2 V Note: 1. V IL min and V IH max are reference only and are not tested. 3 AC Characteristics Applicable over recommended operating range from T A = -40 ° C to +85 ° C, V CC = +1.8V to +5.5V, C L = 1 TTL Gate and 100 pF (unless otherwise noted). 1.8V, 2.7V 5.0V Symbol Parameter Min Max Min Max Units f SCL Clock Frequency, SCL 100 400 kHz t LOW Clock Pulse Width Low 4.7 1.2 µ s t HIGH Clock Pulse Width High 4.0 0.6 µ s t I Noise Suppression Time (1) 100 50 ns t AA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µ s t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.2 µ s t HD.STA Start Hold Time 4.0 0.6 µ s t SU.STA Start Set-up Time 4.7 0.6 µ s t HD.DAT Data In Hold Time 0 0 µ s t SU.DAT Data In Set-up Time 200 100 ns t R Inputs Rise Time (1) 1.0 0.3 µ s t F Inputs Fall Time (1) 300 300 ns t SU.STO Stop Set-up Time 4.7 0.6 µ s t DH Data Out Hold Time 100 50 ns t WR Write Cycle Time 10 10 ms Endurance (1) 5.0V, 25 ° C, Page Mode 1M 1M Write Cycles Note: 1. This parameter is characterized and is not 100% tested. Memory Organization AT34C02, 2K Serial EEPROM: The 2K is internally orga- nized with 256 pages of 1 byte each. Random word addressing requires a 8-bit data word address. STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are seri- ally transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT34C02 features a low-power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by follow- ing these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is nor- mally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). 4 AT34C02 AT34C02 Bus Timing SCL: Serial Clock SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O (1) Note: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5 [ Pobierz całość w formacie PDF ] |
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