AN1272AN1272, Półprzewodniki - dane katologowe, 3.Półprzewodnik
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INTEGRATED CIRCUITS AN1272 UC3842 application note Author: Lester J. Hadley, Jr. 1991 Dec Rev 1: 1996 Apr Philips Semiconductors Application note UC3842 application note AN1272 Author: Les Hadley INTRODUCTION The UC3842 provides all the essential features necessary to the operation of the basic current mode controller. Either a forward or flyback converter may be implemented. The basic differences in these topologies determine special added requirements which, in the flyback or boost converter, relate to stability versus maximum duty cycle. Without varying the ramp oscillator frequency with load, only a constant frequency converter is possible and this is the basis of line current mode converter circuit design example. Duty cycle is a function of load demand up to the limit imposed by the internal duty cycle clamp and, beyond this, output voltage decreases with increased output current demand. With the current mode supply the energy supplied to the inductor or transformer primary (which is proportional to square of the primary current) is continuously monitored by the control loop. There are several different current mode topologies in use, among which are: • Hysteretic terminal and the inverting input, Pin 2. Resistor values in the feedback loop may range from 1k W to 250k W . Output loading must not exceed the source-sink limits stated in the data sheet. Voltage from the error amplification is fed through two diode drops, then further attenuated by a 3:1 resistive divider. This, with the 1V clamp, provides an approximate 0 to 1V reference for the current loop comparator. Pin 2: Error amplifier inverting input. The non-inverting input is fixed at the reference voltage of 2.5V requiring that the feedback voltage be equal to this value under normal operating conditions. Normally a voltage divider is connected between the supply regulated output terminal and ground with a minimum of 1mA of divider current and set for 2.5V out to the error amplifier. Voltage spikes must not exceed V CC positive and 0.7V negative on the feedback line. Open loop testing of the UC3842 in a current mode supply may be implemented as shown in Figure 2 with a potentiometer connected between V REF and ground. Duty cycle may be varied then by varying V2 around the 2.5V level. A synchronous I SENSE signal must be supplied, as shown, to provide duty cycle turn-off. Pin 3: Current sense comparator. The current sense signal provides cycle-by-cycle monitoring of primary switching current in order to provide an active duty-cycle control loop. Figure 3 shows the current sense waveform at Pin 3 versus the output waveform at Pin 6. The Pin 3 maximum voltage to provide current limiting is 1V referenced to ground. When the sense voltage reaches the 1V level, current in primary will no longer increase with increasing load at the supply output, but will allow output voltage to decrease with increased load keeping output current constant. • Constant off time • Constant frequency Hysteretic converters must monitor both peak and valley current. This adds greatly to the circuit complexity but enhances control current accuracy. Constant off time requires more logic to insure variable on-time and a fixed off-time. The latter mode (constant frequency with variable duty cycle and peak current sensing) is the primary converter operating condition addressed in this application note for the UC3842. UC3842 Pin Functions Pin 1: Error amplifier output. (See Figure 1) Closed loop gain and any additional compensation network is connected between this 7(11) (12)7 V CC 34V UVLO 8(14) V REF 5.0V 50mA (9)5 S/R 5V REF GND 6V 16V 2.5V INTERNAL BIAS R T /C T (7)4 OSC 6(10) OUTPUT ERROR AMP S 2R + – (3)2 PWM LATCH V FB R R COMP (1)1 1V CURRENT SENSE COMPARATOR CURRENT SENSE (5)3 5(8) NOTE: Pin numbers in parentheses refer to the D package. SL00185 Figure 1. UC3842 Block Diagram 1991 Dec 2 Rev. 1: 1996 Apr Philips Semiconductors Application note UC3842 application note AN1272 V REF R T A V CC 2N2222 4.7k UC3842 100k 1 8 COMP V REF 0.1 m F ERROR AMP ADJUST 2 7 V FB V CC 0.1 m F 1k 1W 3 6 OUTPUT 5k I SENSE OUTPUT 4.7k I SENSE 5 ADJUST 4 R T /C T GND GND NOTE: High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3. C T SL00190 Figure 2. Open-Loop Test Circuit +V S 8+ ON V R OUTPUT 8 V REF OFF R T 2.8V 4 R T /C T V CL 1.1V ISENSE SIGNAL C T SL01091 Figure 4. Timing Circuit SL01090 Figure 3. Current Sense Waveform Pin 7: Device supply voltage input. A special start-up circuit is recommended (Figure 6) to provide optimum use of the undervoltage lockout capabilities. An initial current of 1mA is necessary to start the device and to activate the internal reference when above 10V, but the output circuit will not become active until V7 reaches the 16V upper threshold. (Voltage feed will operate the device at voltages below 16V after the upper threshold has been exceeded.) This allows a 6V hysteresis range to prevent smaller supply voltage changes from triggering the low voltage lock-out mechanism. Bootstrap operation is dependent upon the dropping resistor, R S , from the main supply bus to Pin 7 to provide the necessary 1mA starting current to activate the voltage reference. A storage capacitor is required as shown in Figure 7 to provide enough energy to kick the output circuit into operation without the V7 voltage decaying below 10V. This imposes a minimum value of capacitance to allow the device to start under full load conditions. The typical value required is 100 Pin 4: Timing network, R T C T . An R/C network is connected between V REF (+5.00V) and ground to provide a fixed time base for the PWM (Figure 4). Ramp peak and valley voltage will have a typical value of 1.1V to 2.8V, respectively, at room temperature. The output waveform at Pin 4 is displayed with Pin 6 output in Figure 5. Pin 5: Device ground. Pin 6: Switching drive output. This output stage provides a maximum of 200mA source and sink current to drive the switching device. This is ideally suited to drive a Power FET with a maximum gate capacitance of 1000pF. A minimum gate voltage of 10V is required to achieve low R ON with the typical Power FET. The Philips UC3842 supplies a 12V minimum output at 200mA. (Reference data sheet for specifications.) NOTE: Bipolar power devices require high sustained base current for low V CE saturation, and minimum deviation. Therefore, an external driver is required for high current bipolar power devices. F. Also critical to successful start-up is a low impedance path from the electrolytic capacitor to Pin 7 and from the bootstrap supply on the transformer. A ceramic m 1991 Dec 3 Philips Semiconductors Application note UC3842 application note AN1272 bypass capacitor is recommended at Pin 7 also to further reduce false under-voltage lockout. [Note, that if a fixed voltage feed is used without a low current start-up and bootstrap supply from the transformer, the snap-off feature with supply overload will not be as readily activated by the device and if supplied from a source separate from the output transformer, will not sense low supply conditions at the transformer primary.] transistors. Device shutdown is activated when Pin 7 voltage drops below the low level lockout threshold of 10V (Figure 9). START-UP HYSTERESIS +V S = 160V ON R S 1mA START OFF 7 100 m F T1 UC3842 C S V R OUTPUT BUK474-200A Q1 ISENSE GND 2.8V R SH +1V 3 5 1.1V I SENSE SIGNAL SL01094 Figure 7. Typical Output Circuit and Hysteresis SL01092 DESIGNING THE CONVERTER Figure 5. Oscillator vs Output A 25W Flyback Example With the flyback converter, energy is stored in the transformer primary flux field during the duty cycle on time. Primary current increases from the initial value at a rate determined by the primary inductance and the primary supply voltage. With current mode control, the maximum primary current under normal operating conditions must first be determined from the converter throughput power and estimated efficiency. For example, 25W converter with a primary supply voltage of 48V and expected efficiency of 75% will require: +V S = 160V R S 1mA START (160 16) Volts 1mA R S 7 = 146k W UC3842 16V TYP. V7 GND 5 V6 SL01093 Figure 6. Calculating the Bootstrap Resistor Pin 8: Voltage reference, 5.0V. An internal band gap reference is provided internally with an overall accuracy of +1% at 1mA external load. An extra 0.5% error results with a 20mA load. The reference has an accuracy versus temperature of 0.4V/ ° C. Typical loading due to the oscillator is <1mA. At start-up the internal reference only becomes active when the supply voltage exceeds the under-voltage upper threshold of 16V versus V8 (Figure 8). As the reference is activated, the UVLO logic then enables the device output SL01095 Figure 8. Power-Up Sequence 1991 Dec 4 Philips Semiconductors Application note UC3842 application note AN1272 T 0.4 I N P I MAX AVE B MAX (Gauss) cm 0.4(3.14) 24 3 1500 AVE T cm 3000 V7 10V 45cm Next, solve for the gap length, GAP T – E AVE GAP (45 7.74) 1500 V6 25 10 3 cm GAP inches 25 10 3 cm 2.24cm in. SL01096 11 mils Note that this is the sum of two gaps in series, so use one-half this value for the shim thickness. (Two core legs in the magnetic path.) The shim (spacer) is made of mylar or other non-metallic material. Calculating the gapped inductance of the primary – Figure 9. Power-Down Sequence Power Out (Watts) eff. (decimal) Power In L P 0.4 N 2 P AVE A E 10 8 25 Watts 0.75 T(cm) 0.4 24 2 1500 0.843 10 8 33.3 Watts 45 Transformer Design Example It is determined to use a Philips EC35-3C8 core set and to add the necessary gap to prevent core saturation. This calculation is derived from the core specifications as listed below for two core halves. (See Philips data on EC35 core.) 203 H The Current Sense Resistor Next, determine peak current in the primary at D MAX (Note: D MAX = duty cycle max.) Let D MAX equal 0.5 and F SW , the oscillator frequency, equal 40kHz. This results in a period, T, of 25 s. Calculating T ON , and I PK – requires an estimated value for primary inductance – choose LP equal 200 m E = 7.74cm, magnetic path length. A E = .843cm 2 , core area. A L = 2250mH/1000T. Ind/Turn m AVE = 1500 (approx). Permeability (Reference Figure [14]) For a primary inductance of 2 00 m H – m H. The primary supply is 48V. I PEAK V S D MAX T ON L P 48V 0.5 25 10 6 sec 205 10 6 H L PRI L REF N PRI N REF 2.9A 1 10 3 200 10 -6 2.25 Next find the value of the shunt resistor necessary to reach the 1V current sense threshold at D MAX = 0.5, 9.47Turns with zero gap core halves R SH 1V 2.9A 0.33 However, this results in nearly 5V/turn. A value of 2V/turn is more optimal. Therefore, recalculating: 48V 2V Turn 24 Turns Calculating power rating – P SHUNT (2.9) 2 (2) D MAX 3 (24) 2 2250mH L P 10 6 1.3mH ungapped inductance 1 3W(ave) (use 1W resistor) The gap length may be calculated from maximum allowable flux, (B MAX = 3000 Gauss from Figure [14]) and peak current (I(DC) plus D Core Losses Core losses at 40kHz and 1500 Gauss (ave) flux are: 1991 Dec 5 (avg) I MAX ), as follows: First find the magnetic path length, – [ Pobierz całość w formacie PDF ] |
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