AN96075AN96075, Półprzewodniki - dane katologowe, 3.Półprzewodnik
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APPLICATION NOTE Using the XA EAn/WAIT pin AN96075 conf Philips Semiconductors Using the XA EAn/WAIT pin Application Note AN96075 Abstract The XA is the high speed 16 bit successor of the 80C51. To be able to use relatively slow (to the XA) 80C51 peripherals a wait state generator is needed. The wait pin on the XA is multiplexed with the EAn function and therefore some precautions has to be taken. The behaviour of this pin is different than on the 80C51, and users must be careful how to use this pin. Purchase of Philips I 2 C components conveys a license under the I 2 C patent to use the com- ponents in the I 2 C system, provided the system conforms to the I 2 C specifications defined by Philips. © Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 2 Philips Semiconductors Using the XA EAn/WAIT pin Application Note AN96075 APPLICATION NOTE Using the XA EAn/WAIT pin AN96075 Author(s): Marco Kuystermans Systems Laboratory Eindhoven, The Netherlands Keywords WAIT, EAn, burstmode, clocksource Date: 1997-03-17 3 Philips Semiconductors Using the XA EAn/WAIT pin Application Note AN96075 Summary To limit the number of pins on the XA some pins have multiple functions. WAIT/EAn is one of them. During RESET the EAn pin determines the memory configuration of the XA. If the XA runs the WAIT function takes over functionality. To use both functions extra hardware is needed. This document describes how to construct this hardware. This document assumes that users are familiar with theXA and its bus interface. 4 Philips Semiconductors Using the XA EAn/WAIT pin Application Note AN96075 CONTENTS 1. THE XA EAN/WAIT PIN................................................................................................................................ 7 1.1 Introduction ........................................................................................................................................... 7 1.2 EAn/WAIT pin design considerations. .................................................................................................... 7 1.3 Generating the EAn signal. .................................................................................................................... 8 1.3.1 Generating EAn using an RC network........................................................................................... 9 1.3.2 Generating EAn using XA reset behaviour .................................................................................. 10 1.3.3 Generating EAn using a D flip-flop .............................................................................................. 11 1.3.4 EAn/WAIT lock up ...................................................................................................................... 13 1.4 Generating WAIT................................................................................................................................. 14 1.4.1 The XA WAIT pin........................................................................................................................ 14 1.4.2 Illegal WAIT configuration ........................................................................................................... 14 1.4.3 Burst and non burst wait state generators ................................................................................... 15 1.4.4 Generating NON burst mode WAIT states .................................................................................. 15 1.4.4.1 Generating non burst WAIT using one shot ...................................................................... 15 1.4.4.2 Generating non burst WAIT using shift register ................................................................ 16 1.4.5 Burst mode wait state generation................................................................................................ 16 1.4.5.1 Burst mode wait state generator using discrete logic ........................................................ 17 1.4.5.2 Burst mode wait state generator using CPLD ................................................................... 17 1.4.5.3 Combining one shot generator with burst detector............................................................ 21 1.4.6 Known problems and solutions.................................................................................................... 23 2. CLOCK SOURCE ....................................................................................................................................... 26 Table of Figures Figure 1, WAIT hold time (2) and WAIT asserted after Strobe asserted (1) _____________________________________ 8 Figure 2, Too short WAIT hold time ___________________________________________________________________ 8 Figure 3, Memory mode hold time_____________________________________________________________________ 8 Figure 4, Generating EAn ___________________________________________________________________________ 9 Figure 5, EAn generator using XA RESET state _________________________________________________________ 10 Figure 6, RESETn and XA control line relationship, 3 = RSTn / 4 = ALE ____________________________________ 10 Figure 7, Generating EAn using D-flip-flop ____________________________________________________________ 11 Figure 8, Generating EAn using RSTn and ALE_________________________________________________________ 12 Figure 9, problem generating EAn solution ____________________________________________________________ 13 Figure 10, Illegal WAIT construction _________________________________________________________________ 14 Figure 11, burst (code) read ________________________________________________________________________ 15 Figure 12: Wait state generator using one shot _________________________________________________________ 15 Figure 13: Wait state generator using shift register ______________________________________________________ 16 Figure 14, wait state generator with address monitor_____________________________________________________ 17 Figure 15, CPLD simulated with number of waitstate = 6 _________________________________________________ 20 Figure 16, Oscilloscope picture with 1 = PSENn, 3 = A1, 4 = A2 and 2 = WAIT_______________________________ 21 Figure 17, burst mode wait state generator with one shot _________________________________________________ 22 Figure 18, WAIT generated too late __________________________________________________________________ 23 Figure 19, relation between strobe/wait/clock __________________________________________________________ 24 Figure 20, Clock source using XTAL__________________________________________________________________ 26 Figure 21, Clock source using XO____________________________________________________________________ 26 Figure 22, Clock source using XO and XTAL2 output ____________________________________________________ 27 5 [ Pobierz całość w formacie PDF ] |
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