AT89C1051UAT89C1051U, Dokumenty i Nauka, Elektronika, Mikrokontrolery, z Flash'em, Atmel
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Features • Compatible with MCS-51 ™ Products • 1K Bytes of Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles • 2.7V to 6V Operating Range • Fully Static Operation: 0 Hz to 24 MHz • Two-level Program Memory Lock • 64 x 8-bit Internal RAM • 15 Programmable I/O Lines • Two 16-bit Timer/Counters • Six Interrupt Sources • Programmable Serial UART Channel • Direct LED Drive Outputs • On-chip Analog Comparator • Low-power Idle and Power-down Modes 8-bit Microcontroller with 1K Byte Flash Description The AT89C1051U is a low-voltage, high-performance CMOS 8-bit microcomputer with 1K byte of Flash programmable and erasable read only memory. It has the same func- tionality and operation as the AT89C1051 with the addition of a UART programmable serial port. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C1051U is a powerful microcomputer which provides a highly-flexible and cost- effective solution to many embedded control applications. The AT89C1051U provides the following standard features: 1K byte of Flash, 64 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level interrupt archi- tecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C1051U is designed with static logic for operation down to zero frequency and supports two software-selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM con- tents but freezes the oscillator disabling all other chip functions until the next hardware reset. AT89C1051U Pin Configuration PDIP/SOIC RST/VPP (RXD) P3.0 (TXD) P3.1 XTAL2 XTAL1 (INT0) P3.2 (INT1) P3.3 (TO) P3.4 (T1) P3.5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 Rev. 1045C–02/00 1 Block Diagram V CC GND RAM ADDR. REGISTER RAM FLASH B REGISTER ACC STACK POINTER PROGRAM ADDRESS REGISTER TMP2 TMP1 BUFFER ALU PC INCREMENTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PROGRAM COUNTER RST TIMING AND CONTROL INSTRUCTION REGISTER DPTR ANALOG COMPARATOR PORT1 LATCH PORT3 LATCH OSC PORT1 DRIVERS PORT3 DRIVERS P1.0 - P1.7 P3.0 - P3.5 P3.7 2 AT89C1051U AT89C1051U Pin Description Each machine cycle takes 12 oscillator or clock cycles. VCC Supply voltage. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. GND Ground. XTAL2 Output from the inverting oscillator amplifier. Port 1 Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require exter- nal pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (I IL ) because of the internal pullups. Port 1 also receives code data during Flash programming and verification. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in . Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in . There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi- mum voltage high and low time specifications must be observed. Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL ) because of the pullups. Port 3 also serves the functions of various special features of the AT89C1051U as listed below: Figure 1. Oscillator Connections Port Pin Alternate Functions P3.0 RXD (serial input port) Note: C1, C2= 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) Figure 2. External Clock Drive Configuration P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) Port 3 also receives some control signals for Flash pro- gramming and verification. RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. 3 Special Function Registers A map of the on-chip memory area called the Special Func- tion Register (SFR) space is shown in the table below. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect. User software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Table 1. AT89C1051U SFR Map and Reset Values 0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H IP XXX00000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0XX00000 0AFH 0A0H 0A7H 98H SCON 00000000 SBUF XXXXXXXX 9FH 90H P1 11111111 97H 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 8FH 80H SP 00000111 DPL 00000000 DPH 00000000 PCON 0XXX0000 87H 4 AT89C1051U AT89C1051U Restrictions on Certain Instructions The AT89C1051U and is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 1K byte of flash program memory. It is fully com- patible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 1K for the AT89C1051U. This should be the responsibility of the software programmer. For example, LJMP 3FEH would be a valid instruction for the AT89C1051U (with 1K of memory), whereas LJMP 410H would not. operation can be found in the Hardware Description section of the Atmel AT89 series flash MCU data book. Note: 1. This feature is not available on the AT89C1051. Program Memory Lock Bits On the chip are two lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection Mode Program Lock Bits LB1 LB2 Protection Type 1 U U No program lock features. 2 P U Further programming of the Flash is disabled. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR. These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 3FFH for the 89C1051U). Violating the physical space lim- its may cause unknown program behavior. CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family archi- tecture have been preserved. 3 P P Same as mode 2, also verify is disabled. Note: 1. The Lock Bits can only be erased with the Chip Erase operation. Idle Mode In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used. It should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. 2. MOVX-related instructions, Data Memory: The AT89C1051U contains 64 bytes of internal data mem- ory. Thus, in the AT89C1051U the stack depth is limited to 64 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is exter- nal PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions men- tioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. Power-down Mode In the power-down mode the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Regis- ters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC Programmable Serial UART Channe The AT89C1051U offers a programmable serial port which is compatible with the serial ports on other AT89 series flash MCU products. A detailed description of the serial port 5 [ Pobierz całość w formacie PDF ] |
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