,
AT89S4D12AT89S4D12, Dokumenty i Nauka, Elektronika, Mikrokontrolery, z Flash'em, Atmel
[ Pobierz całość w formacie PDF ]
AT89S4D12 Features • Compatible with MCS-51 ™ Products • 128K Bytes of In-System Reprogrammable Flash data memory and 4K Bytes of Downloadable Flash Program Memory – Endurance: 1,000 Write/Erase Cycles per Sector – Data Retention: 10 Years • Sector Programming: 128 Bytes/Sector • Single 3.3V ± 10% Supply • On-Chip 12 MHz oscillator • Two-Level Program Memory Lock • 256-Bytes Internal RAM • 5 Programmable I/O Lines • Serial Peripheral Interface (SPI) Channel • Serial Program Downloading • Dual Data Pointer Registers 8-Bit Microcontroller with 132K Bytes Flash Data Memory Description The AT89S4D12 is a low-voltage, highly integrated CMOS 8-bit microcomputer with 4K bytes of downloadable Flash program memory and 128K bytes of in-system repro- grammable Flash data memory. The device is manufactured using Atmel’s high den- sity Flash memory technology and is compatible with the industry-standard MCS-51 ™ instruction set. The 128K bytes of on-chip Flash data memory are accessed as two 64K byte blocks. Bit 0 at SFR location 96H is used to select the active block. The MOVX instruction is used to read and write the data memory. Both the program and data memory arrays can be programmed by an external programmer. The downloadable Flash can be changed one page (128 bytes) at a time and is accessible through the SPI serial peripheral interface port. Holding RESET active forces the SPI bus into a slave input mode and allows the program memory to be writ- ten-from or read-to unless Lock Bit 2 has been activated. The functional operations of the 128K bytes Flash data memory are equivalent to those on the AT29LV010A 1M Bit Flash memory device. AT89S4D12 Pin Configurations SOIC Top View PLCC Top View GND TEST1 RESET SDI/P1.1 SDO/P1.0 TEST2 NC NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC P1.2/DTR P1.3/SCK P1.4/DSR NC NC NC NC NC NC NC NC NC NC P1.0/SDO TEST2 NC NC NC NC NC NC NC 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 P1.4/DSR NC NC NC NC NC NC NC NC 0921A-A–12/97 4-281 Block Diagram V CC GND 128K Flash RAM ADDR. REGISTER RAM 4K FLASH B REGISTER ACC STACK POINTER PROGRAM ADDRESS REGISTER BUFFER TMP2 TMP1 ALU PC INCREMENTER PSW PROGRAM COUNTER TIMING AND CONTROL INSTRUCTION REGISTER DPTR RST PORT 1 LATCH SPI PORT PROGRAM LOGIC 12MHz OSC PORT 1 DRIVERS P1.0 - P1.4 4-282 AT89S4D12 AT89S4D12 Pin Description V CC Supply voltage. GND Ground. Port 1 Port 1 is a 5-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL ) because of the internal pullups. In addition, P1.0, P1.1, and P1.3 can be configured as the SPI data output, data input and shift clock input pins, as shown in the following table. Special Function Registers A map of the on-chip memory area called the Special Func- tion Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect. User software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Memory Con trol Register The MCON register contains the RDY/BSY flag and the most significant Flash address bit A16, for the 128K bytes of on-chip Flash data memory. SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 3) and SPSR (shown in Table 4). The SPI data bits are contained in the SPDR register. Writing the SPI data register during serial data transfer sets the Write Collision bit, WCOL, in the SPSR register. The SPDR is double buff- ered for writing and the values in SPDR are not changed by Reset. Dual Data Pointer Registers To facilitate data transfer, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H - 83H and DP1 at 84H - 85H. Bit DPS = 0 in SFR MCON selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer register. Port Pin Alternate Functions P1.0 SDO (data output pin for SPI channel) P1.1 SDI (data input pin for SPI channel) P1.3 SCK (clock input pin for SPI channel) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. TEST1 TEST1 is set to V CC during downloading of the Flash pro- gram or data memory. This pin can be left unconnected or tied to ground during normal operation. TEST2 Test input. This pin has no user available function and can be left unconnected or tied to ground. 4-283 Table 1. AT89S4D12 SFR Map and Reset Values 0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 SPCR 000X01XX 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H 0BFH 0B0H 0B7H 0A8H SPSR 00000000 0AFH 0A0H 0A7H 98H 9FH 90H P1 XXX11111 MCON XXXXX010 97H 88H 8FH 80H DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 0000000 SPDR XXXXXXXX PCON 0XXX0000 87H 4-284 AT89S4D12 AT89S4D12 Table 2. MCON—Memory Control Register MCON Address = 96H Reset Value = XXXX X010B - - - - - DPS RDY/BSY A16 Bit 7 6 5 4 3 2 1 0 Symbol Function DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the second bank, DP1. RDY/BSY DataFlash Ready/Busy Flag. This b it serves as the RDY/BSY flag in a Read-Only mode during DataFlash write. RDY/BSY = 1 means that the DataFlash is ready t o be programmed. While programming operations are being executed, the RDY/BSY bit equals `0' and is automatically reset to `1' when programming is completed. A16 Memory Block Select. A16 = 0 selects the lower 64K bytes DataFlash memory block. A16 = 1 selects the upper 64K bytes DataFlash block. Table 3. SPCR—SPI Control Register SPCR Address = D5H Reset Value = 000X 01XXB SPIE SPE DORD - CPOL CPHA SPR1 SPR0 Bit 7 6 5 4 3 2 1 0 Symbol Function SPIE SPI Interrupt Enable. This bit, enables SPI interrupts: SPIE = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. SPE SPI Enable. SPI = 1 enables the SPI channel and connects SDO, SDI and SCK to pins P1.0, P1.1, and P1.3. SPI = 0 disables the SPI channel. DORD Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission. CPOL Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control. CPHA Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and slave. Please refer to figure on SPI Clock Phase and Polarity Control. SPR0 SPR1 SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, F OSC ., is as follows: SPR1 0 0 1 1 SPR0 0 1 0 1 SCK = F OSC . divided by 4 16 64 128 4-285 [ Pobierz całość w formacie PDF ] |
Podobne
|